1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to an apparatus and method of calibrating on-die termination for a semiconductor integrated circuit.
2. Related Art
A conventional apparatus for calibrating on-die termination for a semiconductor integrated circuit includes an operation control unit 10, a driver leg 20, a comparing unit 30, an internal code control unit 40, a first counter 50, and a second counter 60, as shown in FIG. 1.
The operation control unit 10 generates various operation control signals, which includes a calibration enable signal ‘cal_enable’, a first amp enable signal ‘1'st_amp_en’, a second amp enable signal ‘2'nd_amp_en’, a second calibration enable signal ‘second_cmp_en’, an internal code pre-update signal ‘internal_regp’, and a final code update signal ‘final_regp’, at predetermined timing according to an on-die termination calibration command ‘odt_calp’. The operation control unit 10 may be composed of an oscillator and a counter.
The driver leg 20 has a structure that functions as an analog/digital converter, and distributes a power supply voltage with a distribution ratio between resistance selected according to an internal code ‘P<0:n>’ and external resistance RQ and outputs a code conversion voltage (zq).
The comparing unit 30 compares the code conversion voltage (zq) with a reference voltage (VREF) according to the first amp enable signal ‘1'st_amp_en’ and the second amp enable signal ‘2'nd_amp_en’, and outputs a comparison result signal ‘comparator_out’.
The internal code control unit 40 receives the calibration enable signal ‘cal_enable’, the first amp enable signal ‘1'st_amp_en’, the second comparison output enable signal ‘second_cmp_en’, the internal code pre-update signal ‘internal_regp’, and the comparison result signal ‘comparator_out’ and outputs an internal code update signal ‘second_regp’. As shown in FIG. 2, the internal code control unit 40 includes a flip flop DFF, an XOR gate XOR1, first and second inverters IV1 and IV2, and first and second NAND gates ND1 and ND2.
The first counter 50 counts the internal code ‘P<0:n>’ according to the internal code update signal ‘second_regp’ and the comparison result signal ‘comparator_out’ and outputs it.
The second counter 60 counts the internal code ‘P<0:n>’ according to the final code update signal ‘final_regp’ or a test mode signal ‘TMs’ and outputs an external code ‘P_LEG<0:n>’. The test mode signal ‘TMs’ is used in a test operation, not in a normal operation. If the test mode signal ‘TMs’ is activated, it is possible to set the external code ‘P_LEG<0:n>’ to a predetermined value.
The operation of a conventional apparatus for calibrating on-die termination for a semiconductor integrated circuit will be described below with reference to FIG. 3.
First, if a system stabilization signal ‘RES’ is activated, an initial on-die termination calibration operation (hereinafter, initial calibration operation) is performed during a predetermined period. Then, a normal on-die termination calibration operation (hereinafter, normal calibration operation) is performed according to a specific command, for example, an auto refresh command. A system outside the semiconductor integrated circuit detects that a voltage and a clock are stably provided and activates the system stabilization signal ‘RES’.
The initial calibration operation is repeatedly performed, for example, several tens of times. The number of times N of the initial calibration operation may be changed according to a circuit design.
If an on-die termination calibration command ‘odt_calp’ is generated once according to the system stabilization signal ‘RES’ or the auto refresh command, the operation control unit 10 shown in FIG. 1 generates the calibration enable signal ‘cal_enable’, the first amp enable signal ‘1'st_amp_en’, the second amp enable signal ‘2'nd_amp_en’, the second calibration enable signal ‘second_cmp_en’, the internal code pre-update signal ‘internal_regp’, and the final code update signal ‘final_regp’ at the predetermined timing.
The calibration enable signal ‘cal_enable’ indicates a point of time when the initial calibration operation is performed and an interval in which the initial calibration operation is performed, and the interval is restricted by a refresh cycle time tRFC. The refresh cycle time tRFC is the predetermined time for continuous input of a command and the auto refresh command, after the system stabilization signal ‘RES’ is activated.
The driver leg 20 outputs the code conversion voltage (zq) according to the internal code ‘P<0:n>’ having an initial value.
The comparing unit 30 compares the code conversion voltage (zq) with the reference voltage (VREF) according to the first amp enable signal ‘1'st_amp_en’ and the second amp enable signal ‘2'nd_amp_en’, which are generated two times in the interval of the calibration enable signal ‘cal_enable’, and outputs the comparison result signal ‘comparator_out’ at a high level or a low level.
Since the first amp enable signal ‘1'st_amp_en’ and the second amp enable signal ‘2'nd_amp_en’ are generated two times in the interval of the calibration enable signal ‘cal_enable’, the comparison operation by the comparing unit 30 is performed two times.
If the comparing unit 30 performs the first comparison operation, the internal code control unit 40 shown in FIG. 2 generates the first internal code update signal ‘second_regp’ according to the second calibration enable signal ‘second_cmp_en’ and the internal code pre-update signal ‘internal_regp’. If the comparing unit 30 performs the second comparison operation and the comparison result signals ‘comparator_out’, which the comparing unit 30 outputs after performing the comparison operation two times, are at the same level, then the internal code control unit 40 prohibits the second internal code update signal ‘second_regp’ from being generated. In contrast, if the comparing unit 30 performs the second comparison operation and the comparison result signals ‘comparator_out’, which the comparing unit 30 outputs after performing the comparison operation two times, are at different levels, then the internal code control unit 40 allows the second internal code update signal ‘second_regp’ to be generated.
If the internal code update signal ‘second_regp’ is generated, then the first counter 50 increases or decreases the internal code ‘P<0:n>’ by 1 step according to the comparison result signal ‘comparator_out’.
If the final code update signal ‘final_regp’ is generated, then the second counter 60 outputs the internal code ‘P<0:n>’ as the external code ‘P_LEG<0:n>’.
On-die termination calibration of a command and address circuit and a data input/output circuit is performed according to the external code ‘P_LEG—<0:n>’.
If the comparison result signals ‘comparator_out’, which the comparing unit 30 outputs after performing the comparison operation two times, are at the same level, then the internal code update signal ‘second_regp’ is generated once, and thus, the external code ‘P_LEG<0:n>’ increases or decreases by 1 step. However, if the comparison result signals ‘comparator_out’, which the comparing unit 30 outputs after performing the comparison operation two times, are respectively at the different levels, then the internal code update signal ‘second_regp’ is generated two times, and the external code ‘P_LEG<0:n>’ increases or decreases. As a result, the external code ‘P_LEG<0:n>’ maintains the same value.
In a conventional apparatus, in a normal calibration interval shown in FIG. 3 where a normal calibration operation is performed, a minimum interval min_2cal where on-die termination calibration is performed two times according to the auto refresh command Auto Ref is two long, and may exceed the interval of the refresh cycle time tRFC. This occurs due to the change in various operation conditions, such as a decrease in the operation preparation time (initial timing) of the semiconductor integrated circuit to perform the initial calibration operation, a decrease in a product operation voltage, and a decrease in the refresh cycle time tRFC. In this case, a normal calibration operation cannot be performed.
A conventional apparatus for calibrating on-die termination for a semiconductor integrated circuit has been described above has the following problems: First, when the voltage difference between the code conversion voltage (zq) and the reference voltage (VREF) is large at during initial operation, the calibration operation is performed two times according to a one-time on-die termination calibration command ‘odt_calp’, but the code updating is only made by 1 step. Accordingly, it takes a long time to adjust the voltage difference between the code conversion voltage (zq) and the reference voltage (VREF) to the offset margin of the comparing unit 30.
Second, it takes a long time to perform the on-die termination calibration operation. Since the on-die termination calibration operation is restricted by the refresh cycle time tRFC, it is difficult to perform the normal calibration operation within the period of the refresh cycle time tRFC.
Third, since it is difficult to perform a normal calibration operation while keeping the predetermined refresh cycle time tRFC, the on-die termination calibration operation according to the auto refresh command may be omitted. However, in this case, in the normal operation state, since the change in the voltage and the temperature is not reflected, and the operation performance of the semiconductor integrated circuit can be adversely affected.